Modern semiconductor integrated circuits typically include several metallization layers. Each metallization layer includes a dielectric layer, for example, of silicon dioxide. Other dielectric materials are being developed, for example, having lower dielectric constants than silica. However, at this time, silica remains the dominant dielectric material, and many of the low-k dielectrics are based on silica with perhaps the addition of some dopants or a significant amount of carbon. For these reasons, the dielectric layer is often simply referred to as the oxide layer. However, some low-k dielectrics being proposed are primarily based on carbon and oxygen with very little silicon.
Contact or via holes are etched through the oxide layer and are thereafter filled with a metal to provide vertical interconnects through the oxide layer to electrically contact an underlying conductive feature. Horizontally extending interconnects are formed over the dielectric layer. A yet higher metallization layer may then be formed on the already formed lower metallization layer. Advanced microprocessors have five or more metallization layers to provide the complex interconnections in a large logic structure.
Vertical interconnects to an underlying semiconductor layer are called contacts while vertical interconnects to an underlying metal layer are called vias. Hereafter, reference will be made only to vias, but the discussion applies with very few changes to contacts. The discussion also applies to other high aspect-ratio holes such as narrow trenches extending fully or partially through an oxide layer.
One of the most demanding steps in the fabrication of semiconductor integrated circuits is the etching of the via holes. The oxide layer is almost always at least 0.7 .mu.m thick and may be as thick as 2 or 3 .mu.m in some situations. However, the extremely dense circuitry of advanced integrated circuits is achieved in part by reducing the width of the vias. A 0.35 .mu.m-wide via is typical for lower levels of modern circuitry. Via widths of 0.25 .mu.m are not uncommon. In newer and planned chips, the via widths are being reduced even further 0.18 .mu.m and below. Contact holes tend to be narrower and have higher aspect ratios than via holes. As a result, such holes have very high aspect ratios, and it is generally difficult to etch a narrow deep hole. Further, because of the high aspect ratios, the via holes must have profile angles approaching 90.degree.. Lastly, the etch must be selective to the photomask defining the etch, and must also be selective to the underlying material, which may be a metal layer or an etch stop layer composed of silicon nitride or titanium nitride, for example.
Nonetheless, etch processes have been developed satisfying these many requirements. Such oxide etching is typically performed as a dry etch process in a plasma etching reactor using a fluorocarbon etching chemistry.
However, a recurring problem in oxide etching is that, under some ill defined conditions, striations are formed in the oxide on the sides of the via holes. Striations are vertically extending non-uniformities generally resembling flutes in a column but with a much rougher and irregular topography. As a result, the via holes have sides that may be very rough. Their formation is illustrated in the sectioned isometric views of FIGS. 1 and 2 showing the selective and anisotropic oxide etching to form a via. A lower oxide layer 10 forming a lower-level dielectric layer is illustrated much thinner than is realistic, and the underlying silicon structure is not illustrated. A metal line 12, for example, of aluminum is formed over the lower oxide layer 10 and is connected through it by unillustrated vias or contacts to the underlying structure. A conformal stop layer 14 of, for example, silicon nitride or titanium nitride, is deposited over the metal line 12 and the lower oxide layer 10. An upper oxide layer 16 is deposited and forms the inter-level dielectric for this level. A photoresist layer 18 is spun onto the upper oxide layer 16 and is photographically patterned to form a photomask aperture 20 over the intended via hole. For advanced lithography, an anti-reflection coating (ARC) is typically disposed between the photoresist layer 18 and the oxide layer 16 to aid the photographic resolution.
Photoresist is typically an organic polymer similar to photographic emulsion that can be exposed to light and developed to form patterns such as the aperture 20. For advanced devices, the photolithographic light is in the spectral range of deep ultraviolet (DUV) around 248 nm. Such DUV photoresists are commercially available from a number of suppliers. Electron or X-ray patterning of the photomask are also known. At this stage of processing prior to the oxide etching, the top photoresist surface 22 and the photoresist sidewalls 24 are smooth although annular ridges often form on the sidewalls arising from interference undulation patterns of the imaging radiation.
After the formation of the photomask, the wafer is transferred to a plasma etch reactor for etching the via hole into the oxide layer 16. Highly selective and anisotropic plasma etch processes are known which etch a vertical hole in the oxide with selectivity to both the photoresist 18 and the nitride layer 14. These processes are typically based on fluorine chemistry, most typically including a fluorocarbon. After the oxide is etched, the photoresist is stripped. However, as shown in FIG. 2, the resulting via hole 26 may be formed with vertically extending striations 28. It is noted that the nitride layer 14 at the bottom of the via hole 26 is usually removed in a separate etch step which may precede or follow the photoresist stripping.
Filling a metal, such as tungsten, into high aspect-ratio via holes is difficult enough when the via sidewalls are smooth. Hole filling becomes much more difficult in the presence of strong striations. Furthermore, striations are generally acknowledged to degrade the performance and reliability of integrated circuits.
The mechanism of the formation of striations is not well understood. It is generally believed that striations initially form on the sidewalls of the apertures in the photolithographic mask and somehow grow and propagate downwardly into the via hole being etched.
Until now, striations have been treated as yet another constraint on the set of useful processing parameters. Just as good selectivity or good profiles are obtained over a processing window that needs to be experimentally determined for as wide a window as possible, so too the processing window must not result in excessive striations. Some parameter values and particular etching gases have been discovered to be excessively prone to striations, and so these are avoided. However, conventionally this determination has been primarily empirical, and each new or revised chemistry requires a redetermination of its susceptibility to striations.
Accordingly, it is desired to provide a processing technique that can be more generally applied to reliably reduce striations in oxide etching.